The invention relates to a method for forming a fine pattern of a semiconductor device using a double patterning method.
Due to rapid distribution of information media such as computers, semiconductor devices have been rapidly developed. The semiconductor devices should simultaneously be operated at high speed and have high storage capacity. As a result, process equipment and technology development have been required to manufacture a semiconductor device having improved integration, reliability, and an electronic characteristic of accessing data with a low manufacturing cost.
A lithography process required to improve the device integration includes an exposure technology using chemically amplified Deep Ultra Violet (DUV) light sources such as ArF (193 nm), VUV (157 nm) or EUV (13 nm), and a technology for developing photoresist materials suitable for the exposure light sources in order to form a pattern having a critical dimension (CD) of less than 0.7 μm.
As semiconductor devices are reduced in size, coating thicknesses of photoresist films are reduced to prevent collapse of a photoresist pattern in a lithography process. Further, multi-mask films having a larger etching selectivity ratio to a lower layer are introduced between an underlying layer and a photoresist film in order to secure an etching selectivity ratio to the patterned lower layer.
FIGS. 1a to 1e are cross-sectional diagrams illustrating a method for forming a fine pattern of a semiconductor device using a conventional double patterning method.
Referring to FIG. 1a, a multi-mask film is formed over an underlying layer 11 of a semiconductor device. The multi-mask films typically comprise a deposition film including an amorphous carbon layer 12, a silicon oxy-nitride film 13, and a polysilicon layer 14.
In order to remove a standing wave of a bottom of a photoresist film, a first bottom anti-reflective coating film 15 is formed over the polysilicon layer 14, and a first positive photoresist pattern 16 is formed over the coating film 15 by a lithography process.
Referring to FIG. 1b, the first bottom anti-reflection layer 15 and the polysilicon layer 14 are patterned with the first photoresist pattern 16 as an etching mask until the silicon oxy-nitride film 13 is exposed. As a result, a first lower anti-reflection coating film pattern 15-1 and a polysilicon pattern 14-1 are formed.
Referring to FIG. 1c, a second lower anti-reflection coating film 18 and a second photoresist film 19 are formed over the polysilicon pattern 14-1 and the exposed silicon oxy-nitride film 13 after a first lower anti-reflection coating film pattern 15-1 and the first photoresist pattern 16 are removed. An exposure process is performed with an exposure mask 20.
Referring to FIG. 1d, the resulting structure is developed to form a second photoresist pattern 19-1.
Referring to FIG. 1e, the second lower anti-reflection coating film 18 and the silicon oxy-nitride film 13 are patterned with the second photoresist pattern 19-1 and the polysilicon pattern 14-1 as an etching mask. As a result, three-layered deposition structures including the silicon oxy-nitride pattern 13-1, the second lower anti-reflection coating film pattern 18-1 and the second photoresist pattern 19-1 are formed between two-layered deposition structures including the polysilicon pattern 14-1 and the silicon oxy-nitride pattern 13-1.
The amorphous carbon layer 12 is etched with the two kinds of deposition structure such as two- and three-layered deposition structures as an etching mask until the underlying layer 11 is exposed.
However, since the conventional method includes forming a photoresist pattern and a lower anti-reflection coating film as an etching mask twice to form an amorphous carbon pattern, manufacturing process steps are actually extremely complicated, thereby increasing the process cost.
Moreover, as the two kinds of the etching mask in etching process to the amorphous carbon layer are used, it is difficult to obtain a uniform pattern profile after the etching process.